The present invention relates generally to electronic circuits, and more particularly, to a power-down signal generating circuit.
Integrated circuits (ICs) include different power domains such as a “core” domain and an “input-output” (IO) domain. The core domain includes a primary power supply and functional circuitry. The primary power supply generates and provides a supply voltage to the core domain. The functional circuitry includes interconnected components such as a processor, a clock generator, and a memory, and generates functional signals.
The IO domain is an I/O interface powered by an IO domain power supply, which generates a secondary supply voltage. The secondary supply voltage usually is at a higher voltage level than the primary supply voltage. The IO domain includes an IO ring that receives the functional signals from the core domain and transmits them to an external circuit or device. When the core is disabled, i.e., when the primary supply voltage is deactivated, the IO domain should switch to a stand-by mode to conserve power. However, as the IO domain does not receive the deactivated primary supply voltage, it may continue to transmit functional signals even when the core is disabled, which causes unnecessary power consumption.
To avoid the aforementioned problem, the IO domain includes a power-down signal generating circuit that generates a power-down signal that indicates if the primary supply voltage has been deactivated. When the primary supply voltage is deactivated, the power-down signal is activated, which switches the IO domain to stand-by mode.
FIG. 1 shows a conventional power-down signal generating circuit 100, which in this case is for an IO ring (not shown) of an IC. The power-down signal generating circuit 100 includes first through fourth transistors 102-108, an amplification circuit 110, and first and second ESD protection circuits 112 and 114. The transistors 102-108 have their gates connected to a first supply voltage VDD by way of the first electrostatic discharge (ESD) protection circuit 112. The first ESD protection circuit 112 receives the first supply voltage VDD from a primary power supply (not shown).
The four transistors 102-108 are connected in series between a second supply voltage VDDE and ground (GND), with first through fourth control signals CS1-CS4 being generated at the drains of the respective first through fourth transistors 102-108. The first through third transistors 102-106 are PMOS pull-up transistors that have weak pull-up and high resistance, while the fourth transistor 108 is an NMOS transistor. A resistor 116 is connected between the drains of the third and fourth transistors 106 and 108.
When the first supply voltage VDD is activated, the first through fourth transistors 102-108 are enabled, which activates the first and second control signals CS1 and CS2, and deactivates the third and fourth control signals CS3 and CS4. More particularly, the first and second control signals CS1 and CS2 acquire an intermediate voltage level between the second supply voltage VDDE and GND, and the third and fourth control signals CS3 and CS4 are pulled to GND. When the first supply voltage VDD is deactivated, the first through third transistors 102-106 are enabled and the fourth transistor 108 is disabled. Thus, the first through fourth control signals CS1-CS4 are activated, i.e., the first through fourth control signals CS1-CS4 are pulled-up to the voltage level of the second supply voltage VDDE.
The amplification circuit 110 is connected directly to the drains of the third and fourth transistors 106 and 108 to receive the third and fourth control signals CS3 and CS4, respectively. The amplification circuit 110 generates a power-down signal CPD. When the third and fourth control signals CS3 and CS4 are inactive, the power-down signal CPD is deactivated, and when the third and fourth control signals CS3 and CS4 are active, the power-down signal CPD is activated and the IO ring switches to a stand-by mode until the power-down signal CPD is deactivated.
A capacitor 118 is connected between the second supply voltage VDDE and the drain of the third transistor 106 (i.e., the node at which CS3 is provided). A fifth transistor 120 has gate, source, and drain terminals connected to the drain terminal of the fourth transistor 108, the drain terminal of the second transistor 104, and a source terminal of a sixth transistor 120, respectively. The sixth transistor 120 has a drain connected to ground (GNDE), and a gate connected to the second ESD protection circuit 114.
When the first supply voltage VDD is activated, the first through fourth transistors 102-108 are simultaneously enabled due to which there is a static leakage current of several micro-amperes, which is disadvantageous, especially in low-power (battery operated) devices, where the static leakage current leads to an increase in the static power consumption. Further, at lower operating voltages, the first through third transistors 102-106 exhibit low switching speed due to the resistance offered by the first through third transistors 102-106. The low switching speed of the first through third transistors 102-106 reduces the operating speed of the power-down signal generating circuit 100.
Therefore, it would be advantageous to have a power-down signal generating circuit with less static leakage current and static power consumption.